Features
• On-chip modules available within the device include
the following features:
• Safety core: Power Architecture® e200Z4 32-bit CPU
with checker core
• Dual issue computation cores: Power Architecture®
e200Z7 32-bit CPU
• 2 MB on-chip code flash (FMC flash) with ECC
• 1.5 MB on-chip SRAM with ECC
• RADAR processing
– Signal Processing Toolbox (SPT) for RADAR signal
processing acceleration
– Cross Timing Engine (CTE) for precise timing
generation and triggering
– Waveform generation module (WGM) for chirp
ramp generation
– 4x 12-bit ΣΔ-ADC with 10 MSps
– One DAC with 10 MSps
– MIPICSI2 interface to connect external ADCs
• Memory Protection
– Each core memory protection unit provides 24
entries
– Data and instruction bus system memory protection
unit (SMPU) with 16 region descriptors each
– Register protection
• Clock Generation
– 40 MHz external crystal (XOSC)
– 16 MHz Internal oscillator (IRCOSC)
– Dual system PLL with one frequency modulated
phase-locked loop (FMPLL)
– Low-jitter PLL to ΣΔ-ADC and DAC clock
generation (not supported on SC66760x devices)
• Functional Safety
– Enables up to ASIL-D applications
– FCCU for fault collection and fault handling
– MEMU for memory error management
– Safe eDMA controller
– Self-Test Control Unit (STCU2)
– Error Injection Module (EIM)
– On-chip voltage monitoring
– Clock Monitor Unit (CMU)
• Security
– Cryptographic Security Engine (CSE2)
– Supports censorship and life-cycle management
• Timers
– Two Periodic Interval Timers (PIT) with 32-bit
counter resolution
– Three System Timer Module (STM)
– Three Software Watchdog Timers (SWT)
– Two eTimer modules with 6 channels each
– One FlexPWM module for 12 PWM signals
• Communication Interfaces
– Two Serial Peripheral interface (SPI) modules
– One LINFlexD module
– Two inter-IC communication interface (I2C)
modules
– One dual-channel FlexRay module with 128
message buffers
– Three FlexCAN modules with configurable buffers -
CAN FD optionally supported on 2 FlexCAN
modules
– One ENET MAC supporting MII/RMII/RGMII
interface
– ZipWire high-speed serial communication
• Debug Functionality
– 4-pin JTAG interface and Nexus/Aurora interface
for serial high-speed tracing
– e200Z7 core and e200Z4 core: Nexus development
interface (NDI) per IEEE-ISTO 5001-2012 Class 3+
• Two analog-to-digital converters (SAR ADC)
– Each ADC supports up to 16 input channels
– Cross Trigger Unit (CTU)
• On-chip voltage DC/DC regulator for core clock (VREG)
• Two Temperature Sensors (TSENS)