1 Features
• Quad-channel multi-protocol linear equalizer
supporting up to 28-GBd (PAM4) and 32-GBd
(NRZ) interfaces
• Suitable for up to CEI-56G, Ethernet (400 GbE),
Fibre Channel (64GFC), InfiniBand™ (HDR), and
CPRI/eCPRI PCB and copper cable applications
• Selectable CTLE boost profiles to compensate
either PCB or cable loss
• Integrated 2×2 crosspoint with pin or register
control for mux, fanout, and signal crossing
• Low power consumption: 160 mW / channel
(typical)
• No heat sink required
• Linear equalization with CTLE for seamless
support of CR/KR link training, auto-negotiation,
and FEC pass-through
• Extends long-reach links by 18-dB+ beyond
normal ASIC-to-ASIC capability at 13.28 GHz
• Eye expander for PAM-4 eye symmetry
enhancement
• Low input-to-output latency: 80 ps (typical)
• Low additive random jitter
• Small 6.00 mm × 6.00 mm BGA package for easy
flow-through routing
• No reference clock required
• Single 2.5-V ± 5% power supply
• –40°C to +85°C ambient temperature range

2 Applications
• Backplane (KR) and midplane C2C attachment
unit interface (AUI) reach extension
• Active copper cables (ACC) (SFP56, QSFP56,
QSFP-DD, or OSFP)
• Mux and de-mux for failover redundancy

3 Description
The DS560MB410 is a low-power, high-performance
four-channel linear equalizer supporting multi-rate,
multi-protocol interfaces up to 28 GBd using fourlevel
pulse amplitude modulation (PAM4), or up to
32 GBd using non-return-to-zero (NRZ) modulation.
It is used to extend the reach and robustness of highspeed
serial links for backplane, midplane, and active
copper cable (ACC) applications. The DS560MB410
can increase the reach between two ASICs by 18+ dB
beyond the normal ASIC-to-ASIC reach.
Each channel operates independently with a userselectable
CTLE boost profile optimized for equalizing
either PCB or copper cable loss profiles. The linear
nature of the DS560MB410’s equalization preserves
input signal characteristics traveling through the
redriver. This transparency allows link partner ASICs
to negotiate Tx equalizer coefficients freely during link
training and to support individual lane Forward Error
Correction (FEC) pass-through in mission mode with
minimal effect on latency.