1 Features
• Dual channel ADC
• 18-bit 10, 25, 65 MSPS ADC
• Noise floor: -160 dBFS/Hz
• Low power and optimized power scaling:
53 mW/ch (10 MSPS) to 94 mW/ch (65 MSPS)
• Latency: 1-2 clock cycles
• 18-bit, no missing codes
• INL/DNL: ±7/ ±0.7 LSB (typical)
• Reference: external or internal
• Input bandwidth: 900 MHz (3-dB)
• Industrial temperature range: -40 to +105°C
• On-chip digital filter (optional)
– Decimation by 2, 4, 8, 16, 32
– 32-bit NCO
• Serial LVDS digital interface (2-, 1- and 1/2-wire)
• Small footprint: 40-QFN (5x5 mm) package
• Spectral performance (fIN = 5 MHz):
– SNR: 83.8 dBFS
– SFDR: 89 dBc HD2, HD3
– SFDR: 101 dBFS Worst spur
• Spectral performance (fIN = 20 MHz):
– SNR: 82.6 dBFS
– SFDR: 85 dBc HD2, HD3
– SFDR: 97 dBFS Worst spur

2 Applications
• High-speed data acquisition
• Industrial monitoring
• Software defined radio
• Power quality analyzer
• Source measurement unit (SMU)
• Communications infrastructure
• Spectrum analyzer
• Control loops
• Instrumentation
• Imaging
• Spectroscopy
• Radar

3 Description
The ADC3681, 82, 83 (ADC368x) is a low noise, ultralow
power 18-bit 65 MSPS high-speed dual channel
ADC family. Designed for lowest noise performance,
it delivers a noise spectral density of -160 dBFS/Hz
combined with excellent linearity and dynamic range.
The ADC368x offers excellent DC precision together
with IF sampling support which makes it suited for a
wide range of applications. High-speed control loops
benefit from the short latency as low as only 1 clock
cycle. The ADC consumes only 94 mW/ch at 65 Msps
and its power consumption scales well with lower
sampling rates.
The ADC368x uses a serial LVDS (SLVDS) interface
to output the data which minimizes the number of
digital interconnects. The device supports two-lane,
one-lane and half-lane options. The ADC36xx is a
pin to pin compatible family of ADCs with 16 and
18-bit resolution and different speed grades. It comes
in a 40-pin QFN package (5 x 5mm) and supports
the extended industrial temperature range from -40 to
+105⁰C.