Product Overview
The VSC8504-02 is a low-power, quad-port Gigabit Ethernet transceiver with four SerDes interfaces for quad-port dual media capability. It also includes an integrated quad port two-wire serial multiplexer (MUX) to control SFPs or PoE modules. It has a low electromagnetic interference (EMI) line driver, and integrated line side termination resistors that conserve both power and printed circuit board (PCB) space.
The VSC8504-02 includes dual recovered clock outputs to support Synchronous Ethernet applications. Programmable clock squelch control is included to inhibit undesirable clocks from propagating and to help prevent timing loops. The VSC8504-02 also supports a ring resiliency feature that allows a 1000BASE-T connected PHY port to switch between master and slave timing without having to interrupt the 1000BASE-T link.

Key Features
This section lists the main features and benefits of the VSC8504-02 device.

Low Power
• Low power consumption of approximately 425 mW per port in 1000BASE-T mode, 200 mW per port
   in 100BASE-TX mode, 225 mW per port in 10BASE-T mode, and less than 115 mW per port in
   100BASE-FX and 1000BASE-X modes
• ActiPHY™ link down power savings
• PerfectReach™ smart cable reach algorithm
• IEEE 802.3az-2010 Energy Efficient Ethernet idle power savings

Advanced Carrier Ethernet Support
• Recovered clock outputs with programmable clock squelch control and fast link failure indication
   (<1 ms; worst-case <3 ms) for G.8261 Synchronous Ethernet applications
• Ring resiliency for maintaining linkup integrity when switching between 1000BASE-T master and
   slave timing
• Supports IEEE 802.3bf timing and synchronization standard
• Integrated quad two-wire serial mux to control SFP and PoE modules
• Support for IEEE 802.3ah unidirectional transport for 100BASE-FX and 1000BASE-X fiber media

Wide Range of Support
• Compliant with IEEE 802.3 (10BASE-T, 100BASE-TX, 1000BASE-T, 100BASE-FX, and
   1000BASE-X) specifications
• Support for >16 kB jumbo frames in all speeds with programmable synchronization FIFOs
• Supports Cisco QSGMII v1.3, Cisco SGMII v1.9, 1000BASE-X MACs, IEEE 1149.1 JTAG boundary
   scan, and IEEE 1149.6 AC-JTAG
• Available in a low-cost, 256-pin BGA package with a 17 mm × 17 mm body size

Flexibility
• VeriPHY® cable diagnostics suite provides extensive network cable operating conditions and status
• Patented, low EMI line driver with integrated line side termination resistors
• Four programmable direct-drive LEDs per port with adjustable brightness levels using register
   controls; bi-color LED support using two LED pins
• Serial LED interface option
• Extensive test features including near end, far end, copper media connector, SerDes MAC/media
   loopback, and Ethernet packet generator with CRC error counter to decrease time-to-market