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STM32F401CDU6 Fiches technique(PDF) 117 Page - STMicroelectronics |
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STM32F401CDU6 Fiches technique(HTML) 117 Page - STMicroelectronics |
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117 / 135 page ![]() DocID025644 Rev 3 117/135 STM32F401xD STM32F401xE Package characteristics 133 Figure 47. WLCSP49 0.4 mm pitch wafer level chip size recommended footprint A2 - 0.380 - - 0.0150 - A3(2) - 0.025 - - 0.0010 - b(3) 0.220 0.250 0.280 0.0087 0.0098 0.0110 D 2.994 3.029 3.064 0.1179 0.1193 0.1206 E 2.994 3.029 3.064 0.1179 0.1193 0.1206 e - 0.400 - - 0.0157 - e1 - 2.400 - - 0.0945 - e2 - 2.400 - - 0.0945 - F - 0.3145 - - 0.0124 - G - 0.3145 - - 0.0124 - aaa - 0.100 - - 0.0039 - bbb - 0.100 - - 0.0039 - ccc - 0.100 - - 0.0039 - ddd - 0.050 - - 0.0020 - eee - 0.050 - - 0.0020 - 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Back side coating 3. Dimension is measured at the maximum bump diameter parallel to primary datum Z. Table 79. STM32F401xCE WLCSP49 wafer level chip size package mechanical data Symbol millimeters inches(1) Min Typ Max Min Typ Max |
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