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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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STM8L151X6 Fiches technique(PDF) 103 Page - STMicroelectronics |
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STM8L151X6 Fiches technique(HTML) 103 Page - STMicroelectronics |
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103 / 146 page  DocID17943 Rev 10 103/146 STM8L151x6/8 STM8L152x6/8 Electrical parameters 123 Figure 37. Typical NRST pull-up current Ipu vs. VDD The reset network shown in Figure 38 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the VIL max. level specified in Table 42. Otherwise the reset is not taken into account internally. For power consumption- sensitive applications, the capacity of the external reset capacitor can be reduced to limit the charge/discharge current. If the NRST signal is used to reset the external circuitry, the user must pay attention to the charge/discharge time of the external capacitor to meet the reset timing conditions of the external devices. The minimum recommended capacity is 10 nF. Figure 38. Recommended NRST pin configuration |
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