ST72561AR7-Auto datasheet(281/324 Pages) STMICROELECTRONICS

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ST72561-Auto

Electrical characteristics

Doc ID 12370 Rev 8

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20.5.2

PLL characteristics

Operating conditions: VDD 3.8 to 5.5V @ TA 0 to 70°C

(a) or V

DD 4.5 to 5.5V @ TA -40 to

125°C

Figure 124. PLL jitter vs signal frequency(1)

Measurement conditions: fCPU = 4 MHz, TA = 25°C

The user must take the PLL jitter into account in the application (for example in serial

communication or sampling of high frequency signals). The PLL jitter is a periodic effect,

which is integrated over several CPU cycles. Therefore, the longer the period of the

application signal, the less it is impacted by the PLL jitter.

Figure 124 shows the PLL jitter integrated on application signals in the range 125 kHz to

2 MHz. At frequencies of less than 125 kHz, the jitter is negligible.

Data characterized but not tested

Table 105.

PLL characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VDD(PLL)

PLL Voltage Range

TA = 0 to +70°C

3.8

5.5

TA = -40 to +125°C4.5

fOSC

PLL input frequency

range

MHz

Δ fCPU/fCPU PLL jitter(1)

Data characterized but not tested.

fOSC = 4 MHz, VDD = 4.5 to

5.5V

See note(2)

Under characterization.

fOSC = 2 MHz, VDD = 4.5 to

5.5V

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

2000

1000

500

250

125

Application Signal Frequency (KHz)

PLL ON

PLL OFF

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