ST72344K2 datasheet(137/247 Pages) STMICROELECTRONICS

137 / 247 page

ST72344xx, ST2345xx

On-chip peripherals

Doc ID 12321 Rev 6

137/247

Framing error

A framing error is detected when:

–

The stop bit is not recognized on reception at the expected time, following either a

de-synchronization or excessive noise.

–

A break is received.

When the framing error is detected:

–

the FE bit is set by hardware

–

Data is transferred from the Shift register to the SCIDR register.

–

No interrupt is generated. However this bit rises at the same time as the RDRF bit

which itself generates an interrupt.

The FE bit is reset by a SCISR register read operation followed by an SCIDR register

read operation.

Figure 65.

SCI baud rate and extended prescaler block diagram

TRANSMITTER

RECEIVER

SCIETPR

SCIERPR

EXTENDED PRESCALER RECEIVER RATE CONTROL

EXTENDED PRESCALER TRANSMITTER RATE CONTROL

EXTENDED PRESCALER

CLOCK

RECEIVER RATE

TRANSMITTER RATE

SCIBRR

SCP1

fCPU

CONTROL

SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0

/PR

/16

CONVENTIONAL BAUD RATE GENERATOR

EXTENDED RECEIVER PRESCALER REGISTER

EXTENDED TRANSMITTER PRESCALER REGISTER

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