STM32F411RET6 datasheet(105/149 Pages) STMICROELECTRONICS

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STM32F411xC STM32F411xE

Electrical characteristics

123

Table 58. I2C characteristics

Symbol

Parameter

Standard mode

I2C(1)(2)

1. Guaranteed by design.

Fast mode I2C(1)(2)

2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to

achieve fast mode I2C frequencies, and a multiple of 10 MHz to reach the 400 kHz maximum I2C fast mode

clock.

Unit

Min

Max

Min

Max

tw(SCLL)

SCL clock low time

4.7

1.3

µs

tw(SCLH)

SCL clock high time

4.0

0.6

tsu(SDA)

SDA setup time

250

100

th(SDA)

SDA data hold time

3450(3)

3. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the

undefined region of the falling edge of SCL.

0900(4)

4. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL

signal.

tr(SDA)

tr(SCL)

SDA and SCL rise time

1000

300

tf(SDA)

tf(SCL)

SDA and SCL fall time

300

th(STA)

Start condition hold time

4.0

0.6

µs

tsu(STA)

Repeated Start condition

setup time

4.7

0.6

tsu(STO)

Stop condition setup time

4.0

0.6

µs

tw(STO:STA)

Stop to Start condition time

(bus free)

4.7

1.3

µs

tSP

Pulse width of the spikes

that are suppressed by the

analog filter for standard fast

mode

050(5)

5. The minimum width of the spikes filtered by the analog filter is above tSP (max)

050(5)

Capacitive load for each bus

line

400

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