MC14499

MOTOROLA

3

CIRCUIT OPERATION

The circuit accepts a 20–bit input, 16 bits for the four–digit

display plus 4 bits for the decimal point — these latter four

bits are optional.

The input sequence is the decimal point code followed by

the four digits, as shown in Figure 1.

In order to enter data the enable input, ENB, must be ac-

tive low. The sample and shift are accomplished on the fal-

ling clock edge, see Figure 2. Data are loaded from the shift

register to the latches when ENB goes high. While the shift

register is being loaded, the previous data are stored in the

latches.

If the decimal point is used, the system requires 20 clock

pulses to load data; otherwise only 16 are required.

CASCADING

The circuit may be cascaded in the following manner.

If a 1111 word is loaded into the decimal point latch, the

output of the shift register is switched to the decimal point

driver, see Figure 3. Therefore, to cascade n four–digit dis-

play drivers, a set–up is used which loads the 1111 cascad-

ing word:

1. ENB = active low.

2. Load 20 bits, the first four bits being 1, with 20 clock

pulses.

3. ENB = high, to load the latch.

4. Repeat steps 1 to 3 (n – 1) times.

5. (n x 20) bits can be loaded into n circuits, with 1111 as

decimal point word to continue the cascading.

SCANNER

The scanner frequency is determined by an on–chip oscil-

lator, which requires an external frequency–determining ca-

pacitor. The capacitor voltage varies between two trigger

levels at the oscillator frequency.

An external oscillator signal can be used, within the recom-

mended operating range of 200 to 800 Hz. For test purposes

this frequency may be increased up to 10 kHz.

A divide by four counter provides four non–overlapping

scanner waveforms corresponding to the four digits — see

Figure 4.

SEGMENT DECODER

The code used in these matrix decoders is shown in Fig-

ure 5.

OUTPUT DRIVERS

There are two different drivers:

• The segment and decimal point drivers; these are NPN

emitter followers with no current limiting devices.

• The digit output buffers; these are short–circuit protected

CMOS devices.

A typical application circuit is shown in Figure 6.

Figure 1. Input Sequence

18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

19

20

3

2

1

TIME

SHIFT

BIT NO.

DIGIT IV

DIGIT III

DIGIT II

DIGIT I

DECIMAL POINT