ST72774 datasheet(101/144 Pages) STMICROELECTRONICS

101 / 144 page

ST72774/ST727754/ST72734

101/144

DDC INTERFACE (Cont’d)

Figure 60. Mapping of DDC1 data structure

DDC2B Transition Mode: This mode avoids the

display switching to DDC2B mode if spurious

noise is detected on SCL while the host is in DDC1

mode.

When the DDC1/2B interface is in DDC1 mode

and detects a falling edge on SCL, it enters the

transition state (see Figure 61).

If a valid I2C sequence (START followed by a valid

Device Address for CF0 =0 (see Table 25)) is not

received within either 128 Vsync pulses or a period

of approximately 2 seconds, then the interface will

revert to DDC1 mode at the EDID start address.

If the interface decodes a valid DDC2B Device

Address, it will lock into DDC2B mode and

subsequently disregard VSYNCI.

When in transition mode, the Vsync pulse counter

or the 2-sec. timeout counter is reset by any

activity on the SCL line.

Figure 61. Transition Mode Waveforms

AHR

ALR

Addr Pointer

0000h

FFFFh

256 * AHR

ALR

128-byte Data

Structure

MSB of ALR is always ‘0’

AHR[7:1]

ALR

Addr Pointer

0000h

FFFFh

512 * AHR[7:1]

ALR

128-byte Data

Structure

DDC v2 mode: CF[1:0] bits = 00b

DDC v2 + P&D mode: CF[1:0] bits = 10b

Reserved

- LSB of AHR is ignored and taken as ‘1’

- MSB of ALR is always ‘0’

Notes:

Note:

Vsync

SDA

SCL

ALR

00h

DDC1 mode

Transition mode

01h

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