MT9072AB datasheet(266/275 Pages) ZARLINK

266 / 275 page

MT9072

Data Sheet

266

Zarlink Semiconductor Inc.

Figure 67 - Receive Basic Frame and E4o Timing

AC Electrical Characteristics - Receive Basic Frame and E4o Timing

Characteristics

Sym.

Min.

Typ.

Max.

Units

Test Conditions

Basic Frame Output Delay

tBD

115

150 pF load on RxBF

Clock Delay

tCD

150 pF load on RxDLC

3E4o Clock High Width

tE4HW

200

150 pF load on RxDLC

3E4o Clock Low Width

tE4LW

150 pF load on RxDLC

Timeslot 31

Bit 8

Timeslot 0

Bit 1

RxBF

(Output)

E2i

Input

RXDL

PCM 30

Bit Cells

E4o - Note 1

(RxDLC Pin)

Output

tCD

Note 1 - The E4o signal is output at the RxDLC Pin when the E4CK control bit (address Y08) is set to one.

Note 2 - The PCM Timeslots are referred to RXDL Output which is delayed 4 bits from the RPOS/RNEG input.

Note3- The E4o Clock(RXDLC Output) is not a 50% duty cycle clock, it will be low for 25 % and high for 75% of the

4.096 MHz clock

tE4HW

tE4LW

tBD

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