MT9072AB datasheet(151/275 Pages) ZARLINK

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MT9072

Data Sheet

151

Zarlink Semiconductor Inc.

F3SM

(0)

Framer 3 Sync and Overflow Mask. This is the mask bit for the F3SVS status bit in the Interrupt

Vector Register (address 910). If this mask bit is one, the corresponding Interrupt Vector status bit

will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

F2HM

(0)

Framer 2 HDLC Mask. This is the mask bit for the F2HVS status bit in the Interrupt Vector

remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

F2EM

(0)

Framer 2 Elastic Mask. This is the mask bit for the F2EVS status bit in the Interrupt Vector

remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

9F2RM

(0)

Framer 2 Rx Line Mask. This is the mask bit for the F2RVS status bit in the Interrupt Vector

remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

8F2SM

(0)

Framer 2 Sync and Overflow Mask. This is the mask bit for the F2SVS status bit in the Interrupt

Vector Register (address 910). If this mask bit is one, the corresponding Interrupt Vector status bit

will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

7F1HM

(0)

Framer 1 HDLC Mask. This is the mask bit for the F1HVS status bit in the Interrupt Vector

remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

6F1EM

(0)

Framer 1 Elastic Mask. This is the mask bit for the F1EVS status bit in the Interrupt Vector

remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

5F1RM

(0)

Framer 1 Rx Line Mask. This is the mask bit for the F1RVS status bit in the Interrupt Vector

remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

4F1SM

(0)

Framer 1 Sync and Overflow Mask. This is the mask bit for the F1SVS status bit in the Interrupt

Vector Register (address 910). If this mask bit is one, the corresponding Interrupt Vector status bit

will remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

3F0HM

(0)

Framer 0 HDLC Mask. This is the mask bit for the F0HVS status bit in the Interrupt Vector

remain inactive (zero). If this mask bit is zero, the corresponding Interrupt Vector status bit will

function normally.

Bit

Name

Functional Description

Table 121 - Interrupt Vector 1 Mask Register (Address 902) (T1)

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