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MT9072AB Fiches technique(PDF) 143 Page - Zarlink Semiconductor Inc

No de pièce MT9072AB
Description  Octal T1/E1/J1 Framer
PDF  275 Pages
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Fabricant  ZARLINK [Zarlink Semiconductor Inc]
Site Internet  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

MT9072AB Fiches technique(HTML) 143 Page - Zarlink Semiconductor Inc

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MT9072
Data Sheet
143
Zarlink Semiconductor Inc.
Bit
Name
Functional Description
15 - 4
#
not used.
3RA(n) Receive Signaling Bits A for Channel n. Where signaling is enabled, these bits are received in
bit position 8 of the 6th DS1 frame (within the 12 frame superframe structure for D4 superframes
and the 24 frame structure for ESF superframes).This data can be overwritten by the microport
for trunk conditioning applications.
2RB(n) Receive Signaling Bits B for Channel n. Where signaling is enabled, these bits are received in
bit position 8 of the 12th DS1 frame (within the 12 frame superframe structure for D4
superframes and the 24 frame structure for ESF superframes).This data can be overwritten by
the microport for trunk conditioning applications.
1RC(n) Receive Signaling Bits C for Channel n. Where signaling is enabled, these bits are transmitted
in bit position 8 of the 18th DS1 frame within the 24 frame structure for ESF superframes. In D4
mode these bits are unused.This data can be overwritten by the microport for trunk conditioning
applications
0RD(n) Receive Signaling Bits D for Channel n. Where signaling is enabled, these bits are transmitted
in bit position 8 of the 24th DS1 frame within the 24 frame structure for ESF superframes. In D4
mode these bits are unused.This data is obtained from the CSTi interface but can be overwritten
via the Micro port for trunk conditioning applications.This data can be overwritten by the
microport for trunck conditioning applications.
Table 110 - Per Channel Receive Signaling Y70-Y87 (T1)



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