ST92185B datasheet(151/178 Pages) STMICROELECTRONICS

No de pièce	ST92185B

Description	16K/24K/32K ROM HCMOS MCU WITH ON-SCREEN-DISPLAY

PDF	178 Pages

Scroll/Zoom	100%

Fabricant	STMICROELECTRONICS [STMicroelectronics]

Site Internet	http://www.st.com

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ST92185B - SERIAL PERIPHERAL INTERFACE (SPI)

SERIAL PERIPHERAL INTERFACE (Cont’d)

Bit 2 = CPHA:

Transmission Clock Phase.

CPHA controls the relationship between the data

on the SDI and SDO pins, and the clock signal on

the SCK pin. The CPHA bit selects the clock edge

used to capture data. It has its greatest impact on

the first bit transmitted (MSB), because it does (or

does not) allow a clock transition before the first

data capture edge. Figure 11 shows the relation-

ship between CPHA, CPOL and SCK, and indi-

cates active clock edges and strobe times.

Bit 1:0 = SPR[1:0]:

SPI Rate.

These two bits select one (of four) baud rates, to

be used as SCK.

Figure 96. SPI Data and Clock Timing

CPOL

CPHA

SCK

(in Figure 11)

(a)

(b)

(c)

(d)

SPR1 SPR0

Clock

Divider

SCK Frequency

(@ INTCLK = 24MHz)

128

256

3000kHz

1500kHz

187.5kHz

93.75kHz

(T = 0.33

µs)

(T = 0.67

µs)

(T = 5.33

µs)

(T = 10.66

µs)

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