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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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PSD813F2 Fiches technique(PDF) 110 Page - STMicroelectronics |
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PSD813F2 Fiches technique(HTML) 110 Page - STMicroelectronics |
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110 / 128 page  AC/DC parameters PSD8XXFX 110/128 Doc ID 7833 Rev 7 tAVPV Address input valid to address output delay (5) 33 35 40 ns tWLMV WR valid to port output valid using macrocell register Preset/Clear (2)(6) 70 70 80 ns 1. Any input used to select an internal PSD function. 2. WR has the same timing as E, LDS, UDS, WRL, and WRH signals. 3. tWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory. 4. Assuming WRITE is active before data becomes valid. 5. In multiplexed mode, latched address generated from ADIO delay to address output on any port. 6. Assuming data is stable before active WRITE signal. Table 59. WRITE timing (3 V devices) (continued) Symbol Parameter Conditions -12 -15 -20 Unit Min Max Min Max Min Max Table 60. Program, WRITE and Erase times (5 V devices) Symbol Parameter Min. Typ. Max. Unit Flash Program 8.5 s Flash Bulk Erase (pre-programmed)(1) 330 s Flash Bulk Erase (not pre-programmed) 5 s tWHQV3 Sector Erase (pre-programmed) 1 30 s tWHQV2 Sector Erase (not pre-programmed) 2.2 s tWHQV1 Byte Program 14 1200 µs Program/Erase cycles (per sector) 100,000 cycles tWHWLO Sector Erase timeout 100 µs tQ7VQV DQ7 valid to output (DQ7-DQ0) valid (data polling)(2) 30 ns 1. The whole memory is programmed to 00h before erase. 2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading. Table 61. Program, WRITE and Erase times (3 V devices) Symbol Parameter Min. Typ. Max. Unit Flash Program 8.5 s Flash Bulk Erase (pre-programmed)(1) 330 s Flash Bulk Erase (not pre-programmed) 5 s tWHQV3 Sector Erase (pre-programmed) 1 30 s tWHQV2 Sector Erase (not pre-programmed) 2.2 s tWHQV1 Byte Program 14 1200 µs Program / Erase Cycles (per sector) 100,000 cycles tWHWLO Sector Erase timeout 100 µs tQ7VQV DQ7 valid to Output (DQ7-DQ0) valid (data polling)(2) 30 ns Obsolete Product(s) - Obsolete Product(s) |
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