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PSD813F2 Fiches technique(PDF) 102 Page - STMicroelectronics

No de pièce PSD813F2
Description  Flash in-system programmable (ISP) peripherals
PDF  128 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

PSD813F2 Fiches technique(HTML) 102 Page - STMicroelectronics

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AC/DC parameters
PSD8XXFX
102/128
Doc ID 7833 Rev 7
tARD
CPLD array
delay
Any macrocell
11
16
22
+ 2
ns
tMIN
Minimum clock
period(2)
tCH+tCL
12
20
30
ns
1.
Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
2.
CLKIN (PD1) tCLCL = tCH + tCL.
Table 50.
CPLD macrocell Synchronous clock mode timing (5 V devices) (continued)
Symbol
Parameter
Conditions
-70
-90
-15
Fast
PT
Aloc
Turbo
off
Slew
rate
(1)
Unit
Min
Max
Min
Max
Min
Max
Table 51.
CPLD macrocell synchronous clock mode timing (3 V devices)
Symbol
Parameter
Conditions
-12
-15
-20
PT
Aloc
Turbo
off
Slew
rate
(1)
Unit
Min Max Min
Max
Min Max
fMAX
Maximum
frequency
External feedback
1/(tS+tCO)
22.2
18.8
15.8
MHz
Maximum
frequency
Internal feedback
(fCNT)
1/(tS+tCO–10)
28.5
23.2
18.8
MHz
Maximum
frequency
Pipelined data
1/(tCH+tCL)
40.0
33.3
31.2
MHz
tS
Input setup time
20
25
30
+ 4
+ 20
ns
tH
Input hold time
0
0
0
ns
tCH
Clock high time
Clock input
15
15
16
ns
tCL
Clock low time
Clock input
10
15
16
ns
tCO
Clock to output
delay
Clock input
25
28
33
– 6
ns
tARD
CPLD array delay
Any macrocell
25
29
33
+ 4
ns
tMIN
Minimum clock
period(2)
tCH+tCL
25
29
32
ns
1.
Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
2.
CLKIN (PD1) tCLCL = tCH + tCL.
Obsolete
Product(s)
- Obsolete
Product(s)



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