DSPIC33FJ06GS101TESLASHML datasheet(213/346 Pages) MICROCHIP

No de pièce	DSPIC33FJ06GS101TE/ML

Description	High-Performance, 16-bit Digital Signal Controllers

PDF	346 Pages

Scroll/Zoom	100%

Fabricant	MICROCHIP [Microchip Technology]

Site Internet	http://www.microchip.com

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213 / 346 page

Preliminary

DS70318D-page 211

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

bit 3-2

CLDAT<1:0>:

Data for PWMxH and PWMxL Pins if CLMODE is Enabled bits

FCLCONx<IFLTMOD> = 0: Normal Fault mode:

If current-limit active, then CLDAT<1> provides data for PWMxH.

If current-limit active, then CLDAT<0> provides data for PWMxL.

FCLCONx<IFLTMOD> = 1: Independent Fault mode:

CLDAT<1:0> is ignored.

bit 1

SWAP<1:0>:

SWAP PWMxH and PWMxL pins

= PWMxH output signal is connected to PWMxL pin and PWMxL signal is connected to PWMxH pins

= PWMxH and PWMxL pins are mapped to their respective pins

bit 0

OSYNC:

Output Override Synchronization bit

= Output overrides via the OVRDAT<1:0> bits are synchronized to the PWM time base

= Output overrides via the OVDDAT<1:0> bits occur on next CPU clock boundary

Note 1:

These bits should be changed only when PTEN = 0. Changing the clock selection during operation will

yield unpredictable results.

DSPIC33FJ06GS101TE/ML Fiches technique(PDF) 213 Page - Microchip Technology