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DSPIC33FJMC202ESS Fiches technique(PDF) 148 Page - Microchip Technology |
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DSPIC33FJMC202ESS Fiches technique(HTML) 148 Page - Microchip Technology |
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148 / 330 page ![]() dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304 DS70283K-page 148 © 2007-2012 Microchip Technology Inc. FIGURE 12-1: TIMER2/3 (32-BIT) BLOCK DIAGRAM(1) FIGURE 12-2: TIMER2 (16-BIT) BLOCK DIAGRAM Set T3IF Equal Comparator PR3 PR2 Reset LSb MSb Note 1: The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register. 2: The ADC event trigger is available only on Timer2/3. Data Bus<15:0> TMR3HLD Read TMR2 Write TMR2 16 16 16 Q Q D CK TGATE 0 1 TON TCKPS<1:0> 2 TCY TCS 1x 01 TGATE 00 T2CK ADC Event Trigger(2) Gate Sync Prescaler 1, 8, 64, 256 Sync TMR3 TMR2 16 TON TCKPS<1:0> Prescaler 1, 8, 64, 256 2 TCY TCS TGATE T2CK PR2 Set T2IF Equal Comparator TMR2 Reset Q QD CK TGATE 1 0 Gate Sync 1x 01 00 Sync |
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