© 2000 Fairchild Semiconductor Corporation

DS006398

www.fairchildsemi.com

August 1986

Revised April 2000

DM74LS164

8-Bit Serial In/Parallel Out Shift Register

General Description

These 8-bit shift registers feature gated serial inputs and

an asynchronous clear. A low logic level at either input

inhibits entry of the new data, and resets the first flip-flop to

the low level at the next clock pulse, thus providing com-

plete control over incoming data. A high logic level on

either input enables the other input, which will then deter-

mine the state of the first flip-flop. Data at the serial inputs

may be changed while the clock is HIGH or LOW, but only

information meeting the setup and hold time requirements

will be entered. Clocking occurs on the LOW-to-HIGH level

transition of the clock input. All inputs are diode-clamped to

minimize transmission-line effects.

Features

s Gated (enable/disable) serial inputs

s Fully buffered clock and serial inputs

s Asynchronous clear

s Typical clock frequency 36 MHz

s Typical power dissipation 80 mW

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

H

= HIGH Level (steady state)

L

= LOW Level (steady state)

X

= Don't Care (any input, including transitions)

↑ = Transition from LOW-to-HIGH level

indicated steady-state input conditions were established.

clock; indicates a one-bit shift.

Order Number

Package Number

Package Description

DM74LS164M

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

DM74LS164N

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Inputs

Outputs

Clear

Clock

A

B

...

LX

X

X

L

L

...

L

HL

X

X

...

H

↑

H

...

H

↑

LX

L

...

H

↑

XL

L

...