DRV8803

SLVSAW5A

– JULY 2011 – REVISED JULY 2011

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Protection Circuits

The DRV8803 is fully protected against undervoltage, overcurrent and overtemperature events.

Overcurrent Protection (OCP)

An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this

(approximately 1.2 ms), then the fault will be automatically cleared. The fault will be cleared immediately if either

RESET pin is activated or VM is removed and re-applied.

Thermal Shutdown (TSD)

If the die temperature exceeds safe limits, all output FETs will be disabled and the nFAULT pin will be driven low.

Once the die temperature has fallen to a safe level, operation will automatically resume.

Undervoltage Lockout (UVLO)

If at any time the voltage on the VM pin falls below the undervoltage lockout threshold voltage, all circuitry in the

device will be disabled, and internal logic will be reset. Operation will resume when VM rises above the UVLO

threshold.

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© 2011, Texas Instruments Incorporated

Product Folder Link(s): DRV8803