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ADAU1373BCBZ-R7 Fiches technique(PDF) 200 Page - Analog Devices |
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ADAU1373BCBZ-R7 Fiches technique(HTML) 200 Page - Analog Devices |
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200 / 296 page ![]() ADAU1373 Rev. 0 | Page 200 of 296 DRC1_CTRL10 REGISTER Address: 0x89, Reset: 0xC0, Name: DRC1_CTRL10 DRC1 Threshold Point Y4 on Y-Axis (Output Level). Table 160. Bit Descriptions for DRC1_CTRL10 Bits Bit Name Settings Description Reset Access [7:0] DRCTHY4 DRC1 Y-Axis Threshold 4. 0xC0 RW 00000000 0 dB 00000001 −0.5 dB 00000010 −1 dB xxxxxxx 0.5 dB step 11000000 −96 dB (default) DRC1_CTRL11 REGISTER Address: 0x8A, Reset: 0x88, Name: DRC1_CTRL11 DRC1 Gain Smoothing Attack and Decay Time Setting |
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