PIC16F720-ESLASHML datasheet(112/244 Pages) MICROCHIP

112 / 244 page

PIC16F/LF720/721

DS41430A-page 112

 2010 Microchip Technology Inc.

15.2

Compare Mode

In Compare mode, the 16-bit CCPR1 register value is

constantly compared against the TMR1 register pair

value. When a match occurs, the CCP1 module may:

• Toggle the CCP1 output

• Set the CCP1 output

• Clear the CCP1 output

• Generate a Special Event Trigger

• Generate a Software Interrupt

The action on the pin is based on the value of the

CCP1M<3:0> control bits of the CCP1CON register.

All Compare modes can generate an interrupt.

FIGURE 15-2:

COMPARE MODE

OPERATION BLOCK

DIAGRAM

15.2.1

CCP1 PIN CONFIGURATION

The user must configure the CCP1 pin as an output by

clearing the associated TRIS bit.

15.2.2

TIMER1 MODE SELECTION

In Compare mode, Timer1 must be running in either

Timer mode or Synchronized Counter mode. The

compare operation may not work in Asynchronous

Counter mode.

15.2.3

SOFTWARE INTERRUPT MODE

When

Software

Interrupt

mode

chosen

(CCP1M<3:0> = 1010), the CCP1IF bit in the PIR1

control of the CCP1 pin (refer to the CCP1CON

15.2.4

SPECIAL EVENT TRIGGER

When

Special

Event

Trigger

mode

chosen

(CCP1M<3:0> = 1011), the CCP1 module does the

following:

• Resets Timer1

• Starts an ADC conversion if ADC is enabled

The CCP1 module does not assert control of the CCP1

pin in this mode (refer to the CCP1CON register).

The Special Event Trigger output of the CCP occurs

immediately upon a match between the TMR1H,

TMR1L register pair and the CCPR1H, CCPR1L

reset until the next rising edge of the Timer1 clock. This

allows

the

CCPR1H,

CCPR1L

pair

effectively provide a 16-bit programmable period

15.2.5

COMPARE DURING SLEEP

The Compare mode is dependent upon the system

clock (FOSC) for proper operation. Since FOSC is shut

down during Sleep mode, the Compare mode will not

function properly during Sleep.

Note:

Clearing the CCP1CON register will force

the CCP1 compare output latch to the

default low level. This is not the PORT I/O

data latch.

CCPR1H CCPR1L

TMR1H

TMR1L

Comparator

Output

Logic

Special Event Trigger

Set CCP1IF Interrupt Flag

(PIR1)

Match

TRIS

CCP1CON<3:0>

Mode Select

Output Enable

Special Event Trigger will:

•

Clear TMR1H and TMR1L registers.

•

NOT set interrupt flag bit TMR1IF of the PIR1 register.

•

Set the GO/DONE bit to start the ADC conversion.

CCP1

Note:

Clocking Timer1 from the system clock

(FOSC) should not be used in Compare

mode. For the Compare operation of the

TMR1 register to the CCPR1 register to

occur, Timer1 must be clocked from the

instruction clock (FOSC/4) or from an

external clock source.

Note 1: The Special Event Trigger from the CCP

module does not set interrupt flag bit

TMR1IF of the PIR1 register.

2: Removing

the

match

condition

changing the contents of the CCPR1H

and CCPR1L register pair, between the

clock edge that generates the Special

Event Trigger and the clock edge that

generates

the

Timer1

Reset,

will

preclude the Reset from occurring.

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