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PC312XDP512F0CFVR Fiches technique(PDF) 556 Page - Freescale Semiconductor, Inc |
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PC312XDP512F0CFVR Fiches technique(HTML) 556 Page - Freescale Semiconductor, Inc |
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556 / 1348 page ![]() Chapter 14 Voltage Regulator (S12VREG3V3V5) MC9S12XDP512 Data Sheet, Rev. 2.21 556 Freescale Semiconductor 14.1.3 Block Diagram Figure 14-1 shows the function principle of VREG_3V3 by means of a block diagram. The regulator core REG consists of two parallel subblocks, REG1 and REG2, providing two independent output voltages. Figure 14-1. VREG_3V3 Block Diagram LVR LVD POR VDDR VDD LVI POR LVR CTRL VSS VDDPLL VSSPLL VREGEN REG2 REG1 PIN VDDA VSSA REG: Regulator Core CTRL: Regulator Control LVD: Low-Voltage Detect LVR: Low-Voltage Reset POR: Power-On Reset API API API: Auto. Periodical Interrupt VBG API Rate Select Bus Clock |
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