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PC312XDP512F0CFVR Fiches technique(PDF) 284 Page - Freescale Semiconductor, Inc |
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PC312XDP512F0CFVR Fiches technique(HTML) 284 Page - Freescale Semiconductor, Inc |
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284 / 1348 page ![]() Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.21 284 Freescale Semiconductor Operation RS – 0 ⇒ NONE (translates to SUB R0, RS, R0) Subtracts zero from the content of register RS using binary subtraction and discards the result. CCR Effects Code and CPU Cycles TST Test Register TST NZ V C ∆∆∆∆ N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000; cleared otherwise. V: Set if a two´s complement overflow resulted from the operation; cleared otherwise. RS[15] & result[15] C: Set if there is a carry from the bit 15 of the result; cleared otherwise. RS1[15] & result[15] Source Form Address Mode Machine Code Cycles TST RS TRI 0 0 0 1 1 0 0 0 RS1 0 0 0 0 0 P |
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