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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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PC312XDP512F0CFVR Fiches technique(PDF) 216 Page - Freescale Semiconductor, Inc |
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PC312XDP512F0CFVR Fiches technique(HTML) 216 Page - Freescale Semiconductor, Inc |
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216 / 1348 page  Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.21 216 Freescale Semiconductor Operation RS1 + RS2 + C ⇒ RD Adds the content of register RS1, the content of register RS2 and the value of the Carry bit using binary addition and stores the result in the destination register RD. The Zero Flag is also carried forward from the previous operation allowing 32 and more bit additions. Example: ADC R6,R2,R2 ADC R7,R3,R3 ; R7:R6 = R5:R4 + R3:R2 BCC ; conditional branch on 32 bit addition CCR Effects Code and CPU Cycles ADC Add with Carry ADC NZ V C ∆∆∆∆ N: Set if bit 15 of the result is set; cleared otherwise. Z: Set if the result is $0000 and Z was set before this operation; cleared otherwise. V: Set if a two´s complement overflow resulted from the operation; cleared otherwise. RS1[15] & RS2[15] & RD[15]new | RS1[15] & RS2[15] & RD[15]new C: Set if there is a carry from bit 15 of the result; cleared otherwise. RS1[15] & RS2[15] | RS1[15] & RD[15]new | RS2[15] & RD[15]new Source Form Address Mode Machine Code Cycles ADC RD, RS1, RS2 TRI 0 0 0 1 1 RD RS1 RS2 1 1 P |
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