PC912XDP512F0CFVR datasheet(209/1348 Pages) FREESCALE

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Chapter 6 XGATE (S12XGATEV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

209

6.8.1.1

Naming Conventions

Destination register, allowed range is R0–R7

RD.L

Low byte of the destination register, bits [7:0]

RD.H

High byte of the destination register, bits [15:8]

RS, RS1, RS2

Source register, allowed range is R0–R7

RS.L, RS1.L, RS2.L

Low byte of the source register, bits [7:0]

RS.H, RS1.H, RS2.H

High byte of the source register, bits[15:8]

Base register for indexed addressing modes, allowed

range is R0–R7

Offset register for indexed addressing modes with

RI+

Offset register for indexed addressing modes with

Allowed range is R0–R7 (R0+ is equivalent to R0)

–RI

Offset register for indexed addressing modes with

Allowed range is R0–R7 (–R0 is equivalent to R0)

NOTE

Even though register R1 is intended to be used as a pointer to the variable

segment, it may be used as a general purpose data register as well.

Selecting R0 as destination register will discard the result of the instruction.

Only the condition code register will be updated

6.8.1.2

Inherent Addressing Mode (INH)

Instructions that use this addressing mode either have no operands or all operands are in internal XGATE

registers:.

Examples

BRK

RTS

6.8.1.3

Immediate 3-Bit Wide (IMM3)

Operands for immediate mode instructions are included in the instruction stream and are fetched into the

instruction queue along with the rest of the 16 bit instruction. The ’#’ symbol is used to indicate an

immediate addressing mode operand. This address mode is used for semaphore instructions.

Examples:

CSEM

; Unlock semaphore 1

SSEM

; Lock Semaphore 3

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