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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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PIC18F44J10 Fiches technique(PDF) 174 Page - Microchip Technology |
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PIC18F44J10 Fiches technique(HTML) 174 Page - Microchip Technology |
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174 / 368 page  PIC18F45J10 FAMILY DS39682E-page 172 © 2009 Microchip Technology Inc. 16.4.4.5 Clock Synchronization and the CKP bit When the CKP bit is cleared, the SCLx output is forced to ‘0’. However, clearing the CKP bit will not assert the SCLx output low until the SCLx output is already sam- pled low. Therefore, the CKP bit will not assert the SCLx line until an external I2C master device has already asserted the SCLx line. The SCLx output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCLx. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCLx (see Figure 16-12). FIGURE 16-12: CLOCK SYNCHRONIZATION TIMING SDAx SCLx DX – 1 DX WR Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SSPxCON CKP Master Device Deasserts Clock Master Device Asserts Clock |
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