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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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HD64F2149YV Fiches technique(PDF) 593 Page - Renesas Technology Corp |
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HD64F2149YV Fiches technique(HTML) 593 Page - Renesas Technology Corp |
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593 / 1075 page  Section 17 Keyboard Buffer Controller Rev. 3.00 Jan 18, 2006 page 565 of 1044 REJ09B0280-0300 Bit 6—Keyboard Clock Out (KCLKO): Controls KBC clock I/O pin output. Bit 6 KCLKO Description 0 Keyboard buffer controller clock I/O pin is low 1 Keyboard buffer controller clock I/O pin is high (Initial value) Bit 5—Keyboard Data Out (KDO): Controls KBC data I/O pin output. Bit 5 KDO Description 0 Keyboard buffer controller data I/O pin is low 1 Keyboard buffer controller data I/O pin is high (Initial value) Bit 4—Reserved: This bit cannot be modified and is always read as 1. Bits 3 to 0—Receive Counter (RXCR3 to RXCR0): These bits indicate the received data bit. Their value is incremented on the fall of KCLK. These bits cannot be modified. The receive counter is initialized to 0000 by a reset and when 0 is written in KBE. Its value returns to 0000 after a stop bit is received. |
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