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HD64F2149YV Fiches technique(PDF) 578 Page - Renesas Technology Corp

No de pièce HD64F2149YV
Description  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1075 Pages
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Fabricant  RENESAS [Renesas Technology Corp]
Site Internet  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F2149YV Fiches technique(HTML) 578 Page - Renesas Technology Corp

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Section 16 I
2C Bus Interface
Rev. 3.00 Jan 18, 2006 page 550 of 1044
REJ09B0280-0300
• Notes on I2C Bus Interface Stop Condition Instruction Issuance
If the rise time of the 9th SCL clock exceeds the specification because the bus load capacitance
is large, or if there is a slave device of the type that drives SCL low to effect a wait, after rising
of the 9th SCL clock, issue the stop condition after reading SCL and determining it to below,
as shown below.
Stop condition
SCL
IRIC
[1] Determination of SCL = Low
9th clock
VIH
High period secured
[2] Stop condition instruction isuuance
SDA
As waveform rise is late,
SCL is detected as low
generation
Figure 16.20 Timing of Stop Condition Issuance



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