H838532H datasheet(314/508 Pages) RENESAS

314 / 508 page

Section 10 Serial Communication Interface

Rev. 1.00 May 30, 2008 Page 294 of 484

REJ09B0436-0100

Bits 1 and 0: Clock select 1, 0 (CKS1, CKS0)

Bits 1 and 0 choose

φ/64, φ/16, φw/2, or φ as the clock source for the baud rate generator.

For the relation between the clock source, bit rate register setting, and baud rate, see section

10.2.8, Bit rate register (BRR).

Bit 1

CKS1

Bit 0

CKS0

Description

φ clock

(initial value)

φ w/2 clock*1/φ w clock*2

φ/16 clock

φ/64 clock

Notes: 1.

φ w/2 clock in active (medium-speed/high-speed) mode and sleep mode

φ w clock in subactive mode and subsleep mode

In subactive or subsleep mode, SCI3 can be operated when CPU clock is

φw/2 only.

10.2.6

Serial Control Register 3 (SCR3)

Bit

Initial value

Read/Write

TIE

R/W

RIE

R/W

MPIE

R/W

CKE0

R/W

TEIE

R/W

CKE1

R/W

SCR3 is an 8-bit register for selecting transmit or receive operation, the asynchronous mode clock

output, interrupt request enabling or disabling, and the transmit/receive clock source.

SCR3 can be read or written by the CPU at any time.

SCR3 is initialized to H'00 upon reset, and in standby, module standby or watch mode.

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