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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AT80SND1C-ROTIL Fiches technique(PDF) 151 Page - ATMEL Corporation |
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AT80SND1C-ROTIL Fiches technique(HTML) 151 Page - ATMEL Corporation |
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151 / 210 page  151 AT8xC51SND1C 4109E–8051–06/03 Interrupt The SPI handles 2 interrupt sources that are the “end of transfer” and the “mode fault” flags. As shown in Figure 118, these flags are combined toghether to appear as a single inter- rupt source for the C51 core. The SPIF flag is set at the end of an 8-bit shift in and out and is cleared by reading SPSTA and then reading from or writing to SPDAT. The MODF flag is set in case of mode fault error and is cleared by reading SPSTA and then writing to SPCON. The SPI interrupt is enabled by setting ESPI bit in IEN1 register. This assumes inter- rupts are globally enabled by setting EA bit in IEN0 register. Figure 118. SPI Interrupt System ESPI IEN1.2 SPI Controller Interrupt Request SPIF SPSTA.7 MODF SPSTA.4 |
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