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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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ST52F510 Fiches technique(PDF) 102 Page - STMicroelectronics |
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ST52F510 Fiches technique(HTML) 102 Page - STMicroelectronics |
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102 / 106 page  ST52F510/F513/F514 102/106 Figure 15.6 Single Master Configuration 15.4.8 Interrupts Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit (SPIE) and the interrupt mask bit (MSKSPI) in the INT_MASK Configuration Register is set. MISO MOSI MOSI MOSI MOSI MOSI MISO MISO MISO MISO SS SS SS SS SS SCK SCK SCK SCK SCK 5V Slave MCU Slave MCU Slave MCU Slave MCU Master MCU Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt SPI End of Transfer Event SPIF SPIE Yes No Master Mode Fault Event MODF Yes No |
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