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TDA2654 Fiches technique(PDF) 7 Page - NXP Semiconductors

No de pièce TDA2654
Description  Vertical deflection circuit
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Fabricant  NXP [NXP Semiconductors]
Site Internet  http://www.nxp.com
Logo NXP - NXP Semiconductors

TDA2654 Fiches technique(HTML) 7 Page - NXP Semiconductors

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November 1982
7
Philips Semiconductors
Product specification
Vertical deflection circuit
TDA2654
APPLICATION INFORMATION (see also Fig.1)
The function is described against the corresponding pin number
1. Blanking pulse output
When the IC is adjusted on a free running frequency of 46 Hz the internal blanking pulse generator delivers a blanking
pulse with a duration between 1,2 ms and 1,5 ms. The circuit is, however, made such that when the flyback time of
the deflection current is longer, the blanking pulse corresponds to the flyback time. The output voltage is also high
when the voltage at pin 9 is lower than nominal 5 V. An external blanking circuit is recommended when tiny-vision
receivers are operated from a car-battery.
2. Synchronization input
The oscillator has to be synchronized by a positive-going pulse. The circuit is made such that synchronization is
inhibited during the flyback time.
3. Oscillator
The oscillator frequency is set by the potentiometer P1 and resistor R2 between pins 3 and 7 and capacitor C1
between pin 3 and ground. For 50 Hz systems the free running frequency is preferably adjusted to 46 Hz.
4. Sawtooth generator
This pin supplies the charging and discharging currents of the capacitor between pin 4 and ground (C2).
5. S-correction and linearity control
The amount of S-correction can be set by the value of C3. For 110
° deflection coils, e.g. AT1040/15, a capacitor of
15
µF will give the right value for S-correction. For 90° deflection systems (e.g. AT1235/00) a nearly linear deflection
current is required, this can be achieved by increasing C3 to 100
µF. The linearity can be adjusted by
potentiometer P2.
6. Output current feedback
To this pin is applied a part of the output current measured across R6 and superimposed on a d.c. voltage derived
from the voltage across the output coupling capacitor. This signal is compared with the internal reference sawtooth.
The internal reference sawtooth has an amplitude of about 0,6 V peak to peak and a d.c. level of about 3,4 V, for a
supply voltage of 25 V at pin 8.
7. Internal voltage divider decoupling
The voltage on this pin is about half the supply voltage at pin 8 and is applied to the bases of emitter followers
supplying the pre-stages of the IC. This voltage controls the amplitude of the internal reference sawtooth. In this way
tracking with the line deflection system is achieved when the supply voltage at pin 8 is derived from the line output
transformer.
8. Positive supply
The value depends on the deflection coil.
9. Output
The deflection coil is connected to ground via coupling capacitor C9 and current sensing resistor R6. The line
frequency superimposed on the output voltage may be too high due to the current feedback system. The line
frequency ripple can be decreased by connecting a resistor across the deflection coil. The flyback time can be
influenced by the resistor divider (R4, R5) for the d.c. feedback to pin 6. It should be noted that the output voltage
shows a negative swing of about 1 V during the first (positive current) part of the flyback.


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