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DAC39RF10 Fiches technique(PDF) 220 Page - Texas Instruments |
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DAC39RF10 Fiches technique(HTML) 220 Page - Texas Instruments |
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220 / 232 page ![]() High Speed Data Inputs Lines Routed on Bo om Layer and Isolated with Ground Figure 9-28. Serdes Bottom Layer Routing with Ground Isolation 10. A reduction in the clock amplitude can degrade the DAC noise performance, so make sure the clock signal has adequate drive strength, especially for high frequencies. To help avoid this, keep the clock source close to the DAC if using a passive balun to drive or interface with the sampling clock pins of the converter. If trace DAC39RF10-SP, DAC39RF10-SEP DAC39RFS10-SP, DAC39RFS10-SEP SBAS932A – MARCH 2024 – REVISED FEBRUARY 2026 www.ti.com 220 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated Product Folder Links: DAC39RF10-SP DAC39RF10-SEP DAC39RFS10-SP DAC39RFS10-SEP |
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