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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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STM32F412RGT3P Fiches technique(PDF) 146 Page - STMicroelectronics |
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STM32F412RGT3P Fiches technique(HTML) 146 Page - STMicroelectronics |
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146 / 201 page  Electrical characteristics STM32F412xE/G 146/201 DocID028087 Rev 7 General PCB design guidelines Power supply decoupling should be performed as shown in Figure 48 or Figure 49, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 48. Power supply and reference decoupling (VREF+ not connected to VDDA) 1. VREF+ and VREF- inputs are both available on UFBGA100. VREF+ is also available on LQFP100. When VREF+ and VREF- are not available, they are internally connected to VDDA and VSSA. |
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