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PIC18F44J10-E/ML Fiches technique(PDF) 271 Page - Microchip Technology

No de pièce PIC18F44J10-E/ML
Description  28/40/44-Pin High-Performance RISC Microcontrollers with nanoWatt Technology
PDF  358 Pages
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Fabricant  MICROCHIP [Microchip Technology]
Site Internet  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F44J10-E/ML Fiches technique(HTML) 271 Page - Microchip Technology

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© 2007 Microchip Technology Inc.
Preliminary
DS39682C-page 269
PIC18F45J10 FAMILY
NEGF
Negate f
Syntax:
NEGF
f {,a}
Operands:
0
≤ f ≤ 255
a
∈ [0,1]
Operation:
( f ) + 1
→ f
Status Affected:
N, OV, C, DC, Z
Encoding:
0110
110a
ffff
ffff
Description:
Location ‘f’ is negated using two’s
complement. The result is placed in the
data memory location ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
≤ 95 (5Fh). See
Section 21.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
NEGF
REG, 1
Before Instruction
REG
=
0011 1010
[3Ah]
After Instruction
REG
=
1100 0110
[C6h]
NOP
No Operation
Syntax:
NOP
Operands:
None
Operation:
No operation
Status Affected:
None
Encoding:
0000
1111
0000
xxxx
0000
xxxx
0000
xxxx
Description:
No operation.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
No
operation
No
operation
No
operation
Example:
None.



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