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STM32H7 Fiches technique(PDF) 307 Page - STMicroelectronics |
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STM32H7 Fiches technique(HTML) 307 Page - STMicroelectronics |
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307 / 357 page ![]() DS12110 Rev 10 307/357 STM32H742xI/G STM32H743xI/G Electrical characteristics (rev V) 320 Figure 105. SPI timing diagram - master mode(1) 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. I2S Interface characteristics Unless otherwise specified, the parameters given in Table 206 for I2S are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 122: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load CL = 30 pF • Measurement points are done at CMOS levels: 0.5VDD • IO Compensation cell activated. • HSLV activated when VDD ≤ 2.7 V • VOS level set to VOS1 Refer to Section 7.3.15: I/O port characteristics for more details on the input/output alternate function characteristics (CK,SD,WS). CPHA=0 MOSI OUTPUT MISO INPUT CPHA=0 LSB OUT LSB IN CPOL=0 CPOL=1 BIT1 OUT NSS input tc(SCK) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) th(MI) High CPHA=1 CPHA=1 CPOL=0 CPOL=1 tsu(MI) tv(MO) th(MO) MSB IN BIT6 IN MSB OUT ai14136c |
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