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STM32H7 Fiches technique(PDF) 284 Page - STMicroelectronics |
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STM32H7 Fiches technique(HTML) 284 Page - STMicroelectronics |
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284 / 357 page ![]() Electrical characteristics (rev V) STM32H742xI/G STM32H743xI/G 284/357 DS12110 Rev 10 General PCB design guidelines Power supply decoupling should be performed as shown in Figure 94 or Figure 95, depending on whether VREF+ is connected to VDDA or not. The 100 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 94. Power supply and reference decoupling (VREF+ not connected to VDDA) 1. VREF+ input is available on all package whereas the VREF– s available only on UFBGA176+25 and TFBGA240+25. When VREF- is not available, it is internally connected to VDDA and VSSA. Figure 95. Power supply and reference decoupling (VREF+ connected to VDDA) 1. VREF+ input is available on all package whereas the VREF– s available only on UFBGA176+25 and TFBGA240+25. When VREF- is not available, it is internally connected to VDDA and VSSA. MSv50648V2 1 μF // 100 nF 1 μF // 100 nF STM32 VREF+ (1) VSSA/VREF- (1) VDDA MSv50649V1 1 μF // 100 nF STM32 VREF+/VDDA (1) VREF-/VSSA (1) |
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