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STM32U535NET3QTR Fiches technique(PDF) 251 Page - STMicroelectronics

No de pièce STM32U535NET3QTR
Description  Ultra-low-power Arm® Cortex®-M33 MCUTrustZone®FPU,240 DMIPS, up to 512 KB flash memory, 274 KB SRAM
PDF  278 Pages
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Fabricant  STMICROELECTRONICS [STMicroelectronics]
Site Internet  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32U535NET3QTR Fiches technique(HTML) 251 Page - STMicroelectronics

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DS14217 Rev 1
251/278
STM32U535xx
Electrical characteristics
253
Figure 56. SAI master timing diagram
Figure 57. SAI slave timing digram
tv(SD_A_MT)
Data output valid
time
Master transmitter (after enable edge), 2.7 V ≤ VDD ≤ 3.6 V
-
19
ns
Master transmitter (after enable edge),
1.71 V ≤ VDD ≤ 3.6 V
-27.5
th(SD_A_MT)
Data output hold
time
Master transmitter (after enable edge)
8
-
1. Evaluated by characterization. Not tested in production.
2. APB clock frequency that must be at least twice SAI clock frequency.
Table 128. SAI characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Max Unit
MS32771V1
SAI_SCK_X
SAI_FS_X
(output)
1/fSCK
SAI_SD_X
(transmit)
tv(FS)
Slot n
SAI_SD_X
(receive)
th(FS)
Slot n+2
tv(SD_MT)
th(SD_MT)
Slot n
tsu(SD_MR)
th(SD_MR)
MS32772V1
SAI_SCK_X
SAI_FS_X
(input)
SAI_SD_X
(transmit)
tsu(FS)
Slot n
SAI_SD_X
(receive)
tw(CKH_X)
th(FS)
Slot n+2
tv(SD_ST)
th(SD_ST)
Slot n
tsu(SD_SR)
tw(CKL_X)
th(SD_SR)
1/fSCK



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