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QB-R5F100SL-TB Fiches technique(PDF) 106 Page - Renesas Technology Corp

No de pièce QB-R5F100SL-TB
Description  True low-power platform (66 μA/MHz, and 0.57 μA for operation with only RTC and LVD) for the general-purpose applications, with 1.6-V to 5.5-V operation, 16- to 512-Kbyte code flash memory, and 41 DMIPS at 32 MHz
PDF  207 Pages
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Fabricant  RENESAS [Renesas Technology Corp]
Site Internet  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

QB-R5F100SL-TB Fiches technique(HTML) 106 Page - Renesas Technology Corp

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RL78/G13
2. ELECTRICAL SPECIFICATIONS (TA = –40 to +85°C)
R01DS0131EJ0350 Rev.3.50
106 of 200
Jun 30, 2020
Notes 1.
The first clock pulse is generated after this period when the start/restart condition is detected.
2.
The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Caution
The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection
register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the values in
the redirect destination.
Remark
The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up
resistor) at that time in each mode are as follows.
Standard mode: Cb = 400 pF, Rb = 2.7 k
Ω



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