KSZ9563RNXI-TR datasheet(177/226 Pages) MICROCHIP

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 2017-2018 Microchip Technology Inc.

DS00002419D-page 177

KSZ9563R

5.2.11.2

Port PTP Transmit Latency Register

5.2.11.3

Port PTP Asymmetry Correction Register

5.2.11.4

Port PTP Egress Timestamp for Request and Delay High Word Register

5.2.11.5

Port PTP Egress Timestamp for Request and Delay Low Word Register

Address:

0xNC02 - 0xNC03

Port N: 1-3

Size:

16 bits

Bits

Description

Type

Default

15:0

PTP Port N TX Latency in Nanoseconds (PTP_TX_LATENCY[15:0])

This field is used to set the fixed transmit delay value from the port N TX time-

stamp to the wire. The default value is 45ns.

R/W

0x002D

Address:

0xNC04 - 0xNC05

Port N: 1-3

Size:

16 bits

Bits

Description

Type

Default

PTP Port N Asymmetry Correction Sign Bit (PTP_ASYM_COR_SIGN)

1 = The magnitude in the PTP_ASM_COR field of this register is negative.

0 = The magnitude in the PTP_ASM_COR field of this register is positive.

R/W

14:0

PTP Port N Asymmetry Correction in Nanoseconds (PTP_ASYM_COR)

This field is used to set the fixed asymmetry value to add in the correction

field for ingress Sync and Pdelay_Resp or to subtract from the correction field

for egress Delay_Req and Pdelay_Req.

R/W

0x0000

Address:

0xNC08 - 0xNC09

Port N: 1-3

Size:

16 bits

Bits

Description

Type

Default

15:0

PTP Port N Egress Timestamp for Pdelay_Req and Delay_Req in

Nanoseconds (XDLY_REQ_TS[31:16])

This field contains the Port N egress timestamp high-word value for Pde-

lay_Req and Delay_Req frames in nanoseconds.

0x0000

Address:

0xNC0A - 0xNC0B

Port N: 1-3

Size:

16 bits

Bits

Description

Type

Default

15:0

PTP Port N Egress Timestamp for Pdelay_Req and Delay_Req in

Nanoseconds (XDLY_REQ_TS[15:0])

This field contains the Port N egress timestamp low-word value for Pde-

lay_Req and Delay_Req frames in nanoseconds.

0x0000

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