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STM32H753II Fiches technique(PDF) 191 Page - STMicroelectronics |
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STM32H753II Fiches technique(HTML) 191 Page - STMicroelectronics |
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191 / 361 page ![]() DS12117 Rev 8 191/360 STM32H753xI Electrical characteristics (rev Y) 318 Figure 48. SPI timing diagram - slave mode and CPHA = 0 tsu(MI) Data input setup time Master mode 2 - - ns tsu(SI) Slave mode 2 - - th(MI) Data input hold time Master mode 1 - - th(SI) Slave mode 1 - - ta(SO) Data output access time Slave mode 9 13 27 tdis(SO) Data output disable time Slave mode 0 1 5 tv(SO) Data output valid time Slave mode, 2.7 V≤VDD≤3.6 V - 11.5 16 Slave mode 1.62 V≤VDD≤3.6 V - 13 20 tv(MO) Master mode - 1 3 th(SO) Data output hold time Slave mode, 1.62 V≤VDD≤3.6 V 9 - - th(MO) Master mode 0 - - 1. Guaranteed by characterization results. Table 105. SPI dynamic characteristics(1) (continued) Symbol Parameter Conditions Min Typ Max Unit MSv41658V1 NSS input CPHA=0 CPOL=0 CPHA=0 CPOL=1 MISO output MOSI input tsu(SI) th(SI) tw(SCKL) tw(SCKH) tc(SCK) tr(SCK) th(NSS) tdis(SO) tsu(NSS) ta(SO) tv(SO) Next bits IN Last bit OUT First bit IN First bit OUT Next bits OUT th(SO) tf(SCK) Last bit IN |
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