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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AM652X Fiches technique(PDF) 234 Page - Texas Instruments |
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AM652X Fiches technique(HTML) 234 Page - Texas Instruments |
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234 / 277 page  SPRS91x_TIMING_PRU_RGMII_RT_07 PRRG12 RGMII_TXC RGMII_TD[3:0] RGMII_TX_CTL PRRG13 SPRS91x_TIMING_PRU_RGMII_RT_06 RGMII_TXC PRRG9 PRRG10 PRRG8 PRRG11 PRRG11 234 AM6548, AM6528, AM6546 AM6526, AM6527 SPRSP08I – NOVEMBER 2017 – REVISED DECEMBER 2019 www.ti.com Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Specifications Copyright © 2017–2019, Texas Instruments Incorporated Figure 5-115. PRU_ICSSG RGMII_RCLK Output Timing Table 5-111. PRU_ICSSG RGMII Switching Characteristics - RGMII_TD[3:0] and RGMII_TCTL NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT PRRG12 tsk(TD-TXC) TD to TXC output skew 10 Mbps - 0.81 0.81 ns 100 Mbps - 0.81 0.81 ns 1000 Mbps - 0.81 0.81 ns tsk(TX_CTL-TXC) TX_CTL to TXC output skew 10 Mbps - 0.81 0.81 ns 100 Mbps - 0.81 0.81 ns 1000 Mbps - 0.81 0.81 ns PRRG13 tt(TD) Transition time, TD 10 Mbps 0.75 ns 100 Mbps 0.75 ns 1000 Mbps 0.75 ns tt(TX_CTL) Transition time, TX_CTL 10 Mbps 0.75 ns 100 Mbps 0.75 ns 1000 Mbps 0.75 ns (1) P = Cycle time Figure 5-116. PRU_ICSSG RGMII_RD[3:0] and RGMII_RCTL Output Timing 5.9.5.21.6.3 PRU_ICSSG MII_RT Electrical Data and Timing NOTE The PRU_ICSSG are contains a second layer of multiplexing to enable additional functionality (including MII functionality) on the PRU GPO and GPI signals. This internal wrapper multiplexing is described in the Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem - Gigabit (PRU_ICSSG) section in Peripherals chapter in the device TRM. NOTE In order to ensure the MII_G_RT I/O timing values published in the device data sheet, the PRU_ICSSG ICSSGn_CORE_CLK (where n = 0 to 2) core clock must be configured for 200 MHz, 225 MHz, or 250 MHz and the TX_CLK_DELAYn (where n = 0 or 1) bit field in the ICSSG_TXCFG0/1 register must be set to 0h (default value). |
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