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56F8167 Fiches technique(PDF) 110 Page - Freescale Semiconductor, Inc

No de pièce 56F8167
Description  16-bit Digital Signal Controllers
PDF  184 Pages
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Fabricant  FREESCALE [Freescale Semiconductor, Inc]
Site Internet  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

56F8167 Fiches technique(HTML) 110 Page - Freescale Semiconductor, Inc

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56F8367 Technical Data, Rev. 7.0
110
Freescale Semiconductor
Preliminary
5.7 Resets
5.7.1
Reset Handshake Timing
The ITCN provides the 56800E core with a reset vector address whenever RESET is asserted. The reset
vector will be presented until the second rising clock edge after RESET is released.
5.7.2
ITCN After Reset
After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled,
except the core IRQs with fixed priorities:
•
Illegal Instruction
•
SW Interrupt 3
•
HW Stack Overflow
•
Misaligned Long Word Access
•
SW Interrupt 2
•
SW Interrupt 1
•
SW Interrupt 0
•
SW Interrupt LP
These interrupts are enabled at their fixed priority levels.



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