ST72F324J2T6 datasheet(116/156 Pages) STMICROELECTRONICS

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OPERATING CONDITIONS (Cont’d)

12.3.3 Operating Conditions with Low Voltage Detector (LVD)

Subject to general operating conditions for VDD, fCPU, and TA.

Notes:

1. Data based on characterization results, not tested in production.

2. When VtPOR is faster than 100 µs/V, the Reset signal is released after a delay of max. 42µs after VDD crosses the

VIT+(LVD) threshold.

3. Applicable only in low voltage devices (planned).

Figure 62. LVD Startup Behaviour

Note: When the LVD is enabled, the MCU reaches its authorized operating voltage from a reset state.

However, in some devices, the reset state is released when VDD is approximately between 0.8V and 1.5V.

As a consequence, depending on the ramp-up speed, the I/Os may toggle when VDD is within this win-

dow.

This may be an issue especially for applications where the MCU drives power components.

Because Flash write access is impossible within this window, the Flash memory contents will not be cor-

rupted.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIT+(LVD)

Reset release threshold

(VDD rise)

VD level = High in option byte

4.0 1)

4.2

4.5

VD level = Med. in option byte3)

VD level = Low in option byte3)

3.55 1)

2.95 1)

3.75

3.15

4.0

3.35

VIT-(LVD)

Reset generation threshold

(VDD fall)

VD level = High in option byte

3.8

4.0

4.25 1)

VD level = Med. in option byte3)

VD level = Low in option byte3)

3.35

2.8

3.55

3.0

3.751)

3.15 1)

Vhys(LVD)

LVD voltage threshold hysteresis 1)

VIT+(LVD)-VIT-(LVD)

150

200

250

VtPOR

VDD rise time

1)2)

∝

µs/V

tg(VDD)

Filtered glitch delay on VDD

Not detected by the LVD

1.5V

VIT+

0.8V

LVD RESET

V D

Window

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