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M66307SP Fiches technique (PDF) - Mitsubishi Electric Semiconductor

M66307SP Datasheet PDF - Mitsubishi Electric Semiconductor
No de pièce M66307SP
Télécharger  M66307SP Télécharger

Taille du fichier   233.48 Kbytes
Page   22 Pages
Fabricant  MITSUBISHI [Mitsubishi Electric Semiconductor]
Site Internet  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor
Description LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS

M66307SP Datasheet (PDF)

Go To PDF Page Télécharger Fiches technique
M66307SP Datasheet PDF - Mitsubishi Electric Semiconductor

No de pièce M66307SP
Télécharger  M66307SP Click to download

Taille du fichier   233.48 Kbytes
Page   22 Pages
Fabricant  MITSUBISHI [Mitsubishi Electric Semiconductor]
Site Internet  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor
Description LINE SCAN BUFFER with 16-BIT MPU BUS COMPATIBLE INPUTS

M66307SP Fiches technique (HTML) - Mitsubishi Electric Semiconductor

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M66307SP Détails du produit

DESCRIPTION
The M66307SP/FP is an integrated circuit consisting of a line buffer with static memory, manufactured by the silicon gate CMOS process, which satisfies A3-paper 400DPI requirements. It converts the stored data from the 16-bit MPU bus into serial data and outputs it at a transfer rate of up to 10Mbps synchronously with the external data request clock or an arbitrary continuous clock.

FEATURES
• 16-bit MPU bus compatible
• Writing data via DMAC is possible
• 320-word (5,120-bit) static RAM
• Data output rate of up to 10Mbps
• Built-in function to add fixed data of a specified length at the beginning of output data (Fixed data: Continuous High bit or Low bit data)
• The output format can be selected between FIFO or LIFO.
• The output method can be selected from two:
   (1) Synchronized with an arbitrary continuous clock (φ IN) on the system side; the frequency of clock output (CLK/φ OUT) can be divided by 1, 2, 4, 8, or 16.
   (2) Synchronized with the data request clock (CLK IN) on the peripheral equipment side.
• Up to two devices can be cascaded.
   (1) Toggle configuration
   (2) 32-bit bus configuration
• High fan-out outputs (CLK/φ OUT, DATA OUT). Io=±24mA
   (±4mA for INTR and DREQ ±8mA for BUSY/ORDY)
• The clock input (CLK/φ IN) contains a Schmitt trigger.
• The reset (RESET), Write (WR) and toggle input (TOG) contain negative noise reduction circuits.

APPLICATION
   Image-handling general OA equipment




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