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WED2DL32512V Fiches technique (PDF) - White Electronic Designs Corporation

WED2DL32512V Datasheet PDF - White Electronic Designs Corporation
No de pièce WED2DL32512V
Télécharger  WED2DL32512V Télécharger

Taille du fichier   146.53 Kbytes
Page   9 Pages
Fabricant  WEDC [White Electronic Designs Corporation]
Site Internet  http://www.whiteedc.com
Logo WEDC - White Electronic Designs Corporation
Description 512Kx32 Synchronous Pipeline Burst SRAM

WED2DL32512V Datasheet (PDF)

Go To PDF Page Télécharger Fiches technique
WED2DL32512V Datasheet PDF - White Electronic Designs Corporation

No de pièce WED2DL32512V
Télécharger  WED2DL32512V Click to download

Taille du fichier   146.53 Kbytes
Page   9 Pages
Fabricant  WEDC [White Electronic Designs Corporation]
Site Internet  http://www.whiteedc.com
Logo WEDC - White Electronic Designs Corporation
Description 512Kx32 Synchronous Pipeline Burst SRAM

WED2DL32512V Fiches technique (HTML) - White Electronic Designs Corporation

WED2DL32512V Datasheet HTML 1Page - White Electronic Designs Corporation WED2DL32512V Datasheet HTML 2Page - White Electronic Designs Corporation WED2DL32512V Datasheet HTML 3Page - White Electronic Designs Corporation WED2DL32512V Datasheet HTML 4Page - White Electronic Designs Corporation WED2DL32512V Datasheet HTML 5Page - White Electronic Designs Corporation WED2DL32512V Datasheet HTML 6Page - White Electronic Designs Corporation WED2DL32512V Datasheet HTML 7Page - White Electronic Designs Corporation WED2DL32512V Datasheet HTML 8Page - White Electronic Designs Corporation WED2DL32512V Datasheet HTML 9Page - White Electronic Designs Corporation

WED2DL32512V Détails du produit

DESCRIPTION
The WEDC SyncBurst - SRAM family employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process. WEDC’s 16Mb SyncBurst SRAMs integrate two 512K x 16 SRAMs into a single BGA package to provide 512K x 32 configuration. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CLK). The synchronous inputs include all addresses, all data inputs, active LOW chip enable (CE), burst control input (ADSC) and byte write enables (BW0-3). Asynchronous inputs include the output enable (OE), clock (CLK) and snooze enable (ZZ). There is also a burst mode input (MODE) that selects between interleaved and linear burst modes. Write cycles can be from one to four bytes wide, as controlled by the write control inputs. Burst operation can be initiated with the address status controller (ADSC) input.

FEATURES
■ Fast clock speed: 200, 166, 150 & 133MHz
■ Fast access times: 2.5ns, 3.5ns, 3.8ns & 4.0ns
■ Fast OE access times: 2.5ns, 3.5ns, 3.8ns 4.0ns
■ Single +3.3V power supply (VDD)
■ Separate +3.3V or +2.5V isolated output buffer supply (VDDQ)
■ Snooze Mode for reduced-power standby
■ Single-cycle deselect
■ Common data inputs and data outputs
■ Individual Byte Write control and Global Write
■ Clock-controlled and registered addresses, data I/Os and control signals
■ Burst control (interleaved or linear burst)
■ Packaging:
   • 119-bump BGA package
■ Low capacitive bus loading




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